1. Field of Invention
The present invention relates to a phase lock loop. More particularly, the present invention relates to a method for reducing phase lock time and jittering of a phase lock loop and a phase lock loop using the same.
2. Description of Related Art
The research and development of phase lock loops (PLL) has started a long time and it is still the focus of today's research because of PLL's widespread application and high development potential. Wherein, there are many advantages of PLL being improved or upgraded continuously, such as the increased frequency, improved stability, expanded frequency range, and reduced lock time etc.
To be brief, the basic function of a phase lock loop is to drive a device of variable frequency using an oscillator with very low frequency variation as basic reference through the feedback function of a close loop control system, so as to keep the device having the same phase with the oscillator quickly and constantly, i.e. phase locked.
FIG. 1A illustrates the structure of a conventional phase lock loop, which includes five sub circuit systems: a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, and a frequency divider FD. The phase frequency detector PFD is used for detecting the difference between a reference signal REF and a frequency-dividing signal DS, and converts the comparison result into two digital signals to respectively output a pull-up signal DH and a pull-down signal DL. The charge pump CP is used for converting the two digital signals into a control voltage and outputting the control voltage. The loop filter LF can filter the high frequency portion of the control voltage. The voltage controlled oscillator VCO converts the control voltage into an oscillation signal VO and outputs the oscillation signal VO. The frequency divider FD lowers the frequency and sends it back to the phase frequency detector PFD to be compared with the reference signal REF.
FIG. 1B is a detailed circuit diagram of the charge pump CP. Referring to FIG. 1B, the circuit includes a capacitor C, a pull-up current source lup, a pull-down current source ldn, a pull-up switch Sup and a pull-down switch Sdn. When the output phase lags, the pull-up switch Sup is on, the pull-down switch Sdn is off, the pull-up current source lup charges the capacitor C to raise the output voltage VO, and the output voltage VO is sent to the voltage controlled oscillator VCO after being filtered by the loop filter LF, so as to increase the oscillation frequency of the voltage controlled oscillator VCO.
When a phase lock loop of quick phase locking function is to be designed, the driving capabilities of the pull-up current source lup and the pull-down current source ldn of the charge pump CP as shown in FIG. 1B are to be increased; that is, the driving currents of the two current sources are to be increased. Accordingly, the charge/discharge rate of the charge pump CP to the capacitor is increased. Thus, at re-starting, the voltage sent by the charge pump CP to the voltage controlled oscillator VCO raises quickly; accordingly the frequency raises quickly, so as to lock phase quickly.
However, this design has a major defect. The frequency may exceed the originally designed frequency when increasing quickly, and when it is sent back to the phase frequency detector PFD through the frequency divider FD, the phase frequency detector PFD outputs a signal to turn on the pull-down switch Sdn in the charge pump CP to discharge the capacitor C. The driving capability of the pull-down current source ldn is increased and extra current is pulled down, so that the capacitor C is discharged too fast, the output voltage is too low, and the frequency therefore decreases too much. As it continues, frequency jittering will occur, which extends the phase lock time, or even blocks the phase and frequency to be locked.